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www.altera.com/enpirion enpirion ? power datasheet en5335qi 3a powersoc voltage mode synchronous buck pwm dc - dc converter with integrated inductor 3 - pin programmable output description th e en5335qi is a power system on a chip (powersoc). it is specifically designed to meet the precise voltage and fast transient requirements of present and future high- performance, low-power processor, dsp, fpga, memory boards and system level applications in a distributed power architecture. advanced circuit techniques, ultra high switching frequency, and very advanced, high-density, integrated circuit and proprietary inductor technology deliver high- quality, ultra compact, non-isolated dc- dc conversion. operating this converter requires as few as three external components that include small value input and output ceramic capacitors and a soft-start capacitor. the altera enpirion solution significantly helps in system design and productivity by offering greatly simplified board design, layout and manufacturing requirements. in addition, a reduction in the number of vendors required for the complete power solution helps to enable an overall system cost savings. all altera enpirion products are rohs compliant and lead-free manufacturing environment compatible. typical application circuit figure 1. simple layout. features ? integrated inductor, mosfets, controller ? footprint 1/3 rd that of competing solutions ? low part count: only 3 mlc capacitors ? up to 10w continuous output power ? 5mhz operating frequency ? high efficiency, up to 93% ? v out accuracy 3% over line, load and temp ? wide input voltage range of 2.375v to 6.6v ? 3-pin vid output voltage select to choose one of 7 pre-programmed voltage levels ? output enable pin and power ok signal ? programmable soft-start time ? programmable over-current protection ? thermal shutdown, short circuit, and uvlo ? output over-voltage protection ? rohs compliant, msl level 3, 260c reflow applications ? point of load regulation for low-power processors, network processors, dsps, fpgas, and asics ? notebook computers, servers, workstations ? broadband, networking, lan/wan, optical ? low voltage, distributed power architectures with 2.5v, 3.3v or 5v rails ? dsl, stb, dvr, dtv, ipc ? ripple sensitive applications ordering information part number temp rating (c) package en5335qi - 40 to +85 44 - pin qfn t&r EVB-EN5335QI qfn evaluation board vid output voltage select v out v in vsense 47? f 15nf vout vs 0 vs 1 vs 2 pok pgnd agnd ss pvin avin 22 ? f 00846 october 11, 2013 rev j
en5335qi 2 www.altera.com/enpirion pin configuration below is a top view diagram of the en5335qi package. note: nc pins are not to be electrically connected to each other or to any external signal, ground, or voltage. however, they must be soldered to the pcb. failure to follow this guideline may result in part malfunction or dama ge. figure 2. pin-out diagram, top view. 00846 october 11, 2013 rev j
en5335qi 3 www.altera.com/enpirion pin descriptions pin name function 1 - 3 nc no connect C C C C C C 00846 october 11, 2013 rev j
en5335qi 4 www.altera.com/enpirion block diagram figure 3. system block diagram. absolute ma ximum ratings caution: absolute maximum ratings are stress ratings only. functional operation beyond recommended operating conditions is not implied. stress beyond absolute maximum ratings may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. maximum electrical ratings min max voltages on: v in , v out - 0.3v 7.0v voltages on: v sense - 0.3v v in + 0.3v voltages on: v s0 - v s2 (n ote 1) - 0.3v v in + 0.3v voltages on: enable - 0.3 v v in + 0.3v maximum thermal ratings ambient operating range - 40c +85c storage temperature range - 65c +150c reflow peak body temperature msl3 (10 sec) +260c note 1 : v s0 -v s2 pins have an internal pull-up resistor, only ground potentials should be placed on them as required. (+) (-) error amp v out p-drive n-drive uvlo thermal limit current limit soft start sawtooth generator (+) (-) pwm comp pvin enable compensation network bandgap reference pgnd voltage selector vs0 vs1 vs2 vsense eain eaout rocp ss reference voltage selector comp over voltage power good logic over voltage v out pok 00846 october 11, 2013 rev j
en5335qi 5 www.altera.com/enpirion recommended operating conditions parameter symbol min max units input voltage range (for output voltages < 1.2v) v in 2.375 5.5 v input voltage range (for output voltages 1.2v) v in 2.375 6.6 v en5335qi operating amb ient temperature t a - 40 +85 c operating junction temperature t j - 40 +125 c thermal characteristics parameter symbol typ units thermal shutdown t sd 150 c thermal shutdown hysteresis t sdh 15 c thermal resistance: junction to case (0 lfm) (note 2) ? jc 3 c/w thermal resistance: junction to ambient (0 lfm) ? ja 25 c/w note 2 : based on a four-layer board and proper thermal design in line with jedec eij/jesd 51 standards. electrical characteristics note: v in =5.5v over operating temperature range unless otherwise noted. typical values are at t a = 25c. parameter symbol test conditions min typ max units operating input voltage (for output voltages < 1.2v) v in 2.375 5.5 v operating input voltage (for output voltages 1.2v) v in 2.375 6.6 v v out initial accuracy ? v out_ init t a = 25c, v in = 5.0v, i load = 0 a; ? all vid settings except 0.8v ? 0.8v - 2 - 3 +2 +2 % vid output voltage settings v out vs2 vs1 vs0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 3.3 2.5 1.8 1.5 1.25 1.2 0.8 reserved v drop out voltage v in - v out drop out voltage at full load 600 mv shut - down supply current i s enable=0v 100 ? a switching frequency f osc 5 mhz v out output voltage regulation v out over line, load and temperature vid output voltage setting (v): 1.2, 1.25, 1.5, 1.8, 2.5, 3.3 0.8v - 3.0 - 4.0 3.0 4.0 % maximum continuous output current over current trip piont i ocp 4.5 a 00846 october 11, 2013 rev j
en5335qi 6 www.altera.com/enpirion parameter symbol test conditions min typ max units enable operation disable thre shold v disable max voltage to ensure the converter is disabled 0.8 v enable threshold v enable 2.375v v in 5.5v 5.5v < v in 1.8 2.0 v enable pin current i enable v in = 5.5v 50 ? a voltage select operation vs x logic low threshold v sx - low threshold voltage for logic low 0.8 v vs x logic high threshold v sx - high threshold voltage for logic hig h (internally pulled high; can be left floating to achieve logic high) 1.8 v in v vs x pin current i vsx (v in = 5.5v) vsx = gnd vsx = v in vsx = open 50 0 0 ? a power ok operation pok low voltage v pok i pok = 4ma (sink current) 0.4 v max pok voltage v p ok v in v typical performance characteristics efficiency versus load, v in = 5.0v efficiency versus load, v in = 3.3v 50 55 60 65 70 75 80 85 90 95 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 lo a d c urre nt ( a ) efficiency (%) v in =5.0v v out = 3.3v v out = 2.5v v out = 1.8v v out = 1.5v v out = 1.2v 50 55 60 65 70 75 80 85 90 95 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 lo a d c urre nt ( a ) efficiency (%) v in =5.0v v out = 3.3v v out = 2.5v v out = 1.8v v out = 1.5v v out = 1.2v 50 55 60 65 70 75 80 85 90 95 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 lo a d c urre nt ( a ) efficiency (%) v in =3.3v v out = 0.8v v out = 2.5v v out = 1.8v v out = 1.5v v out = 1.2v 50 55 60 65 70 75 80 85 90 95 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 lo a d c urre nt ( a ) efficiency (%) v in =3.3v v out = 0.8v v out = 2.5v v out = 1.8v v out = 1.5v v out = 1.2v 00846 october 11, 2013 rev j
en5335qi 7 www.altera.com/enpirion load transient, 0 C 3a, v in /v out = 5.5v/1.2v load transient, 0 C 3a, v in /v out = 5.5v/3.3v sta rt -up waveform, v in /v out = 5.5v/1.2v shut-down waveform, v in /v out = 5.5v/1.2v 00846 october 11, 2013 rev j
en5335qi 8 www.altera.com/enpirion theory of operation synchronous buck converter the en5335qi is a synchronous, pin programmable power supply with integrated power mosfet switches and integrated inductor. the nominal input voltage range is 2.4- 5.0v. the output can be set to common pre-set voltages by connecting appropriate combinations of 3 voltage selection pins to ground. the feedback control loop is a type iii voltage-mode and the part uses a low-noise pwm topology. up to 3a of output current can be drawn from this converter. the 5mhz operating frequency enables the use of small-size output capacitors. the power supply has the following protection features: ? over-current protection (to protect the ic fr om excessive load current) ? thermal shutdown with hysteresis ? over-voltage protection ? under-voltage lockout circuit to disable the converter output when the input voltage is less than approximately 2.2v additional features include: ? soft-start circuit, limiting the in-rush current when the converter is powered up ? power good circuit indicating whether the output voltage is within 90% - 120% of the programmed voltage output voltage programming the en5335qi output voltage is programmed using a 3-pin voltage- id or vid selector. three binary vid pins allow the user to choose one of seven pre-set voltages. refer to table 1 for the proper vid pin settings to choose vout. the voltage select pins, vs0, vs1, and vs2, are pulled -up internally and so will default to a logic high, or 1, if left open. connecting the voltage select pin to ground will result in a logic 0. table 1: output voltage select table: vs2* vs1* vs0* output voltage 0 0 0 3.3v 0 0 1 2.5v 0 1 0 1.8v 0 1 1 1.5v 1 0 0 1.25v 1 0 1 1. 2v 1 1 0 0.8v 1 1 1 reserved input capacitor selection the en5335qi requires about 20uf of input capacitance. low-cost, low-esr ceramic capacitors should be used as input capacitors for this converter. the dielectric must be x5r or x7r rated. in some a pplications, lower value capacitors are needed in parallel with the larger, capacitors in order to provide high frequency decoupling. it is recommended to use 10v rated mlcc capacitors. table 2. recommended input capacitors. description mfg p/n 10 uf, 10v, 10% x7r, 12 06 (2 capacitors needed) murata taiyo yuden grm3 1cr71a106ka01l lmk316b7106kl - t 22 uf, 10v, 10% x 7 r, 1210 (1 capacitor needed) murata taiyo yuden grm32er71a 226ke20l lmk325b7226km - t output capacitor selection the en5335qi has been optimized for use with approximately 50f of output capacitance. low esr ceramic capacitors are required with x5r or x7r rated dielectric formulation. y5v or equivalent dielectric formulations must not be used as these lose capacitance with frequency, temperature and bias voltage. output ripple voltage is determined by the aggregate output capacitor impedance. output impedance, denoted as z, is comprised of effective series resistance, esr, and effective series inductance, esl: z = esr + esl. 00846 october 11, 2013 rev j
en5335qi 9 www.altera.com/enpirion placing output capacitors in parallel reduces the impedance and will hence result in lower ripple voltage. typical ripple versus capacitance is given below: output capacitor configuration typical output ripple (mvp - p) (as measured on en5335qi evaluation board) 1 x 47 uf 3 0 3 x 22 uf 1 5 table 3. recommended output capacitors. description mfg p/n 22 uf, 6.3v, 10% x 5 r, 1206 (3 capacitors needed) murata taiyo yuden grm31 cr60j226ke19l jmk316bj226kl - t 47 uf, 10 v, 10% x5r, 12 10 47uf, 6.3v, 10% x5r, 1210 (1 capacitor needed) murata avx grm3 2er61a476ke20l 12106d476kat2 a enable operation the enable pin provides a means to shut down the device, or enable normal operation. a logic high will enable the converter into normal operation. when the enable pin is asserted, the device will undergo a normal soft start. a logic low will disable the converter and cause it to shut down. when enable goes low, circuitry internal to the device continue to operate to ensure the output voltage is gradually returned to zero and the circuits turn off subsequently. a short low going pulse on enable is ignored. soft-start operation soft start is a method to reduce in-rush current when the device is enabled. the output voltage is ramped up slowly upon start-up. the output rise time is controlled by choice of a soft-start capacitor, which is placed between the ss pin (pin 37) and the agnd pin (pin 29). rise time: t r = c ss * 75 k? during start-up of the converter, the reference voltage to the error amplifier is gradually increased from zero to its final level by an internal current source of typically 10ua. typical soft-start rise time is 1ms to 3ms. the rise time is measured from the time when avin > v uvlo and the enable signal crosses its logic high threshold. typical ss capacitor values are in the range of 15nf to 50 nf. power- up /down sequencing during power-up, enable should not be asserted before pvin, and pvin should not be asserted before avin. the pvin should never be powered when avin is off. during power down, the avin should not be powered down before the pvin. tying pvin and avin or all three pins (avin, pvin, enable) together during power up or power down meets these requirements . pre-bias start- up the en53 35 qi does not support startup into a pre-biased condition. be sure the output capacitors are not charged or the output of the en53 35 qi is not pre- biased when the en5335qi is first enabled. pok operation the pok signal is an open drain signal from the converter indicating the output voltage is within th e specified range. the pok signal will be a logic high when the output voltage is within 90% - 120% of the programmed output voltage. if the output voltage goes outside of this range, the pok signal will be a logic low until the output voltage has returned to within this range. in the event of an over-voltage condition the pok signal will go low and will remain in this condition until the output voltage has dropped to 95% of the programmed output voltage before returning to the high state (see also: over- vo ltage protection). n total zzzz 1 ... 111 21 ???? 00846 october 11, 2013 rev j
en5335qi 10 www.altera.com/enpirion over-current protection the current limit function is achieved by sensing the current flowing through the sense p- mosfet. when the sensed current exceeds the current limit, both nfet and pfet switches are turned off. if the over-current condition is removed, the over-current protection circuit will enable the pwm operation. this circuit is designed to provide high noise immunity. the nominal over current trip point is set to 4.5a. it is possible to increase the over-current set point by about 50% by connecting a 7.5k ? resistor between rocp (pin 27) and gnd. the typical voltage at the rocp pin is 0.75v. in some cases, such as the start-up of fpga devices, it is desirable to blank the over-current protection feature. in order to disable over- current protection, the rocp pin should be tied to any voltage between 2.5v and pvin. over-voltage protection when the output voltage exceeds 120% of the programmed output voltage, the pwm operation stops, the lower n-mosfet is turned on and the pok signal goes low. when the output voltage drops below 95% of the programmed output voltage, normal pwm operation resumes and pok returns to its high state. thermal overload protection thermal shutdown will disable operation once the junction temperature exceeds approximately 150oc. once the junction temperature drops by approx 25oc, the converter will re-start with a normal soft-start. input under-voltage lock-out circuitry is provided to ensure that when the input voltage is below the specified voltage range, the converter will not start-up. circuits for hysteresis, input de-glitch and output leading edge blanking are included to ensure high noise immunity and prevent false tripping. compensation the en5335qi is internally compensated through the use of a type 3 compensation network and is optimized for use with about 50 f of output capacitance and will provide excellent loop bandwidth and transient performance for most applications. (see the section on capacitor selection for details on recommended capacitor types.) voltage mode operation provides high noise immunity at light load. in some cases modifications to the compensation may be required. for more information, contact altera power applications support. 00846 october 11, 2013 rev j
en5335qi 11 www.altera.com/enpirion layout recommendation figure 4 shows critical components and layer 1 traces of a recommended minimum footprint en 5335 qi layout. alternate enable configurations and other small signal pins need to be connected and routed according to specific customer application. please see the gerber files on the altera website www.altera.com/enpirion for exact dimensions and other layers. please refer to figure 4 while reading the layout recommendations in this section. recommendation 1: input and output filter capacitors should be placed on the same side of the pcb, and as close to the en 5335 qi package as possible. they should be connected to the device with very short and wide traces. do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. the +v and gnd traces between the capacitors and the en 5335 qi should be as close to each other as possible so that the gap between the two nodes is minimized, even under the capacitors. recommendation 2: two pgnd pins are dedicated to the input circuit, and two to the output circuit. the slit in figure 4 separating the input and output gnd circuits helps minimize noise coupling between the converter input and output switching loops. recommendation 3: the system ground plane should be the first layer immediately below the surface layer. this ground plane should be continuous and un-interrupted below the converter and the input/output capacitors. please see the gerber files on the altera website www.altera.com/enpirion . recommendation 4 : the large thermal pad underneath the component must be connected to the system ground plane through as many vias as possible. figure 4: top pcb layer critical components and copper for minimum footprint the drill diameter of the vias should be 0.33mm , and the vias must have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20-0.26mm. do not use thermal reliefs or spokes to connect the vias to the ground plane. this connection provides the path for heat dissipation from the converter. please see figures: 7, 8, and 9. recommendation 5 : multiple small vias (the same size as the thermal vias discussed in recommendation 4 should be used to connect ground terminal of the input capacitor and output capacitors to the system ground plane. it is preferred to put these vias under the capacitors along the edge of the gnd copper closest to the +v copper. please see figure 4. these vias connect the input/output filter capacitors to the gnd plane, and help reduce parasitic inductances in the input and output current loops. if the vias cannot be placed under c in and c out , then put them just outside the capacitors along the gnd slit separating the two components. do not use thermal reliefs or spokes to connect these vias to the ground plane. recommendation 6 : avin is the power supply for the internal small-signal control circuits. it should be connected to the input voltage at a quiet point. in figure 4 this connection is made at 00846 october 11, 2013 rev j
en5335qi 12 www.altera.com/enpirion the input capacitor close to the v in connection. recommendation 7 : the layer 1 metal under the device must not be more than shown in figure 4. see the section regarding exposed metal on bottom of package. as with any switch- mode dc/dc converter, try not to run sensitive signal or control lines underneath the converter package on other layers. recommendation 8: the vsense point should be just after the last output filter capacitor. keep the sense trace as short as possible in order to avoid noise coupling into the control loop. 00846 october 11, 2013 rev j
en5335qi 13 www.altera.com/enpirion design considerations for lead - frame based modules exposed metal on bottom of package lead frame offers many advantages in thermal performance, in reduced electrical lead resistance, and in overall foot print. however, they do require some special considerations. in the assembly process lead frame construction requires that, for mechanical support, some of the lead -frame cantilevers be exposed at the point where wire-bond or internal passives are attached. this results in several small pads being exposed on the bottom of the package. only the large thermal pad and the perimeter pads are to be mechanically or electrically connected to the pc board. the pcb top layer under the en5335qi should be clear of any metal except for the large thermal pad. the grayed - out area in figure 5 represents the area that should be clear of any metal (traces, vias, or planes), on the top layer of the pcb. figure 6 shows the recommended pcb footprint for this device. figure 5. lead-frame exposed metal. grey area highlights exposed metal that is not to be mechanically or electrically connected to the pc b. 00846 october 11, 2013 rev j
en5335qi 14 www.altera.com/enpirion figure 6: en5335 qi pcb footprint (top view) the solder stencil aperture for the thermal pad is shown in blue and is based on enpirion power product manufacturing specifications. 00846 october 11, 2013 rev j
en5335qi 15 www.altera.com/enpirion package dimensions figure 7 . package dimensions contact information altera corporation 101 innovation drive san jose, ca 95134 phone: 408- 544 -7000 www.altera.com ? 2013 altera corporation confidential. all rights reserved. altera, arria, cyclone, enpirion, hardcopy, max, megacore, nios, quartus and stratix words and logos are trademarks of altera corporation and registered in the u.s. patent and trademark office and in other countries. all other words and logos identified as trademarks or service marks are the property of their respective holders a s described at www.altera.com/common/legal.html. altera warrants pe rformance of its semiconductor products to current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to i n writing by altera. altera customers are advised to obtain the latest version of device specifications before relying on any publi shed information and before placing orders for products or services. 00846 october 11, 2013 rev j

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